Metal-oxide-semiconductor (MOS) circuits have two classes of logic families: static and dynamic. Static and dynamic logic families operate differently. Static logic comprises a load device and a driver which performs a logic function. Typically, in PMOS or NMOS technology, the load device is a constant current source which is always turned on in one logic state and therefore dissipates power. CMOS technology reduces, but does not eliminate, the amount of power dissipated.
Dynamic logic comprises precharge circuitry and circuitry which performs a logic function. Typically, dynamic logic is used in MOS circuits for low-power synchronous applications.
FIG. 1a is a schematic of an exemplary NMOS dynamic circuit. In this and the following schematics, the following conventions are used. A dot, i.e., ".cndot.", inside the transistor is placed closest to the transistor's source. A p-channel transistor has an "o" on its gate, while an n-channel transistor has no "o." If a substrate wire is not shown, for an n-channel transistor the substrate connects to ground, and for a p-channel transistor, the substrate connects to the power supply voltage Vcc. NMOS circuits use n-channel transistors and PMOS circuits use p-channel transistors. CMOS circuits use both n-channel and p-channel transistors.
FIG. 1b is a timing diagram of the clock pulses input to the exemplary circuit of FIG. 1a. This NMOS dynamic circuit uses clocked logic having two phases, .phi..sub.1 and .phi..sub.2. The clock signals .phi..sub.1 and .phi..sub.2 are input to the gates of transistors T1 and T2, respectively. Logic signals A and B are input to the gates of transistors T3 and T4, respectively. The logic circuit shown in FIG. 1a functions as a NAND gate. Its output signal, i.e., Vout, is equal to Not(A.multidot.B). One phase .phi..sub.1 of the clock signals turns on the active load T1 and precharges the output node V.sub.OUT to a "high" voltage (e.g., Vcc-Vth, where Vth is the threshold voltage of transistor T1). The second phase .phi..sub.2 of the clock signals discharges the output node V.sub.OUT if the input logic is appropriate, i.e., if A and B are both "high."
FIG. 1c is a schematic of the exemplary circuit of FIG. 1a using a CMOS implementation. CMOS circuits can operate with a single phase clock. Unlike the implementation of FIG. 1a, transistor T1 is a PMOS transistor in this implementation. The gates of T1 and T2 both connect to the clock input .phi..sub.0 to simultaneously charge the output node Vout and discharge Vout if the input logic is appropriate. Dynamic circuits are used in memory and microprocessor circuits. For example, dynamic circuits can be used in command decoders, command predecoders, and control circuits. Dynamic circuits have low power dissipation and synchronous operation.
A dynamic random access memory (DRAM) is a semiconductor device for storing digital information. Data, as digital information, can be written to and read from a DRAM. DRAMS can be fabricated using MOS integrated circuit technology.
FIG. 2 is a schematic of a DRAM memory cell 100. A DRAM has many memory cells. Typically, each memory cell comprises a combination of a transistor 101 and a capacitor C 103. In the storage cell, digital information is represented by a charge stored in the capacitor C 103. When the memory cell 100 stores a "1" value, the capacitor 103 is charged, and when the memory cell 100 stores a "0" value, the capacitor is discharged. However, the present invention is equally applicable when a charged capacitor is used to store a "0" value and a discharged capacitor is used to store a "1" value.
The capacitor C 103 will lose any charge stored by the capacitor unless it is regularly recharged or refreshed. Also, reading the information stored in the memory cell 100 destroys the contents of the memory cell 100. More specifically, after a memory cell 100 that previously had a charged capacitor has been read, the amount of charge remaining on the capacitor is not sufficient to distinguish it from a memory cell having a discharged capacitor. As a result, the information previously stored in the memory cell needs to be restored after it has been read. Also, the memory cell needs to be periodically refreshed to prevent the information stored by the memory cell from being lost due to charge leakage.
Each memory cell 100 is connected to a word-line (WL) 105 and a bit-line 107. A word-line driver restores the contents of the memory cell 100. To restore a "one" level to the memory cell capacitor C 103, the word line driver must output a voltage on the word line 105 that exceeds the voltage present on the bit-line 107. Since the maximum voltage that will be present on the bit line 107 after a read operation is the supply voltage Vcc, the word line driver must generate a voltage that exceeds Vcc. Typically, the word line driver is a charge pump circuit that generates a voltage that exceeds the supply voltage Vcc. The charge pump circuit typically includes an oscillator that generates a series of pulses.
As the bit density and number of memory cells in a DRAM increases, the complexity of the DRAM increases. DRAMs use dynamic circuits to reduce power consumption. In addition, DRAMs use pulse generators and oscillators to perform various functions such as charge pumping, and the outputs of the pulse generators are often combined to generate one or more additional pulses.
FIG. 3 is a schematic of a typical circuit 300 to combine two pulses. In this and the following schematics, the following additional conventions are used. The numbers beneath the reference character near the transistor indicate the transistor's preferred width and length. For example, n-channel transistor M2 has a width of 10 microns and a length of 0.5 microns.
In FIG. 3, pulses IN1 and IN2 are input to NAND gates 301 and 302 respectively. The other input of each NAND gate 301, 302 connects to Vcc causing the NAND gates 301, 302 to act like invertors. The outputs of NAND gates 301 and 302 are called node N1 and node N2 respectively. P-channel transistor M10 connects in series with n-channel transistors M2 and M4 to form a NAND gate. The source of M10 connects to Vcc and the source of M4 connects to ground. The outputs of NAND gates 301 and 302 are connected to the gate of n-channel transistors M2 and M4, respectively. In addition, the output of NAND gate 302 connects to the gate of p-channel transistor M10. The drain of M10 connects to the input of inverter I1 at node N4. The output of inverter I1 on node N5 is the output of the pulse generator. The source of p-channel transistor MS connects to Vcc, the drain of MS connects to node N4, and the gate of MS connects to node N5.
FIGS. 4a, 4b and 4c are timing diagrams of the prior art circuit 300 of FIG. 3. FIG. 4a is a timing diagram showing the output of the pulse generator 300, node N5, when input pulses IN1 and IN2 are in phase. When IN1 is high, node N1 is low. When node N1 is low, transistor M2 is not conducting current and the drain of M2 presents a high impedance. Similarly, when IN2 is high, node N2 is low. When node N2 is low, transistor M4 is not conducting current; however, transistor M10 does conduct current and node N4 goes high, to voltage level Vcc. When node N4 is high, the output of inverter I1, node N5, goes low. When node N5 is low p-channel transistor MS is "on" thereby pulling up the input to inverter I1 to Vcc.
When IN1 is low, node N1 is high. When node N1 is high, transistor M2 conducts current. When IN2 is low, node N2 is high. When node N2 is high, transistor M4 conducts current and transistor M10 is "off." When nodes N1 and N2 are both high, transistors M2 and M4 are both "on" and node N4 goes "low," i.e., to ground. When node N4 goes low, the output of inverter I1, i.e., node N5, goes high thereby turning off transistor M8s.
For slow DRAMs having a long cycle time, the circuit of FIG. 3 generates a pulse of sufficient duration. However, in large, fast DRAMS, signal path lengths are often unequal, signal loads are often not exactly matched, both of which cause signals that should have identical timing to be skewed with respect to each other. As a result, the circuit of FIG. 3 sometimes has a problem if used in high density, fast DRAMS to generate a pulse from the combination of two input pulses.
FIG. 4b shows the output pulse at node N5 when input pulses IN1 and IN2 are skewed or out-of-phase with respect to each other. FIG. 4c shows the output pulse at node N5 when input pulses IN1 and IN2 are skewed to the point where IN1 and IN2 are almost 180.degree. out of phase. As the skew between IN1 and IN2 increases, the width of the pulse output at node N5 decreases. The narrow width of the output pulse at node N5 causes problems. In FIG. 4c, the output pulse at node N5 has pulse width of about two nanoseconds (ns) and is not sufficient to precharge a dynamic circuit or to provide a sufficient duration input pulse to a charge pump, a latch or register. As a result, the dynamic circuit can enter a meta-stable state and malfunction.
Therefore, a method and apparatus are needed to guarantee a sufficiently long pulse width when combining input pulses.